Real-time adaptive control for best ic performance

ABSTRACT

The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands ( 30 ). Each island ( 30 ) is controlled and its working conditions are modified depending on some parameters. The remainder of the chip is controlled as well, depending on other parameters. This requires that each island ( 30 ) has a local controller ( 36 ) communicating with a global controller ( 42 ). The main control parameters are e.g. supply voltage, threshold voltage and clock frequency.

The present invention relates to real-time adaptive control for bestIntegrated Circuit (IC) performance as well as to an IC with suchcontrol and a controller for performing such control.

The failure of sub-micrometer technologies to continue with constantprocess tolerances gives origin to significant challenges for designtechnologies for process and litho variability. As the variation offundamental parameters such as channel length, threshold voltage, thinoxide thickness and interconnect dimensions goes well beyond acceptablelimits, new circuit topologies, logic and layout optimizations mustaccount for signal and supply noise, thermal gradients, EMI andsubstrate coupling.

Research efforts in this focus area delve into the incorporation ofreal-time adaptive schemes for the minimization of process and lithovariability effects and improvement of timing and signal integrityclosure. While process spreads are tightly controlled, their impact oncircuit design and behavior is higher and higher. For instance, whilebefore a variation of 100 mV on a threshold voltage Vt with regard to anominal threshold voltage Vt of 450 mV was not that crucial, in deepsub-micron technologies with a nominal threshold voltage Vt of 350 mV a100 mV variation can make circuit design quite difficult.

In traditional design for manufacturability schemes, a manufacturabilityanalysis is performed when the layout is ready. If the operational yieldis not high enough a diagnosis is carried out to either correct theprocess or the design. Experience gained from this type of analysisprovides a direct feedback path to the circuit design stage, usually inthe form of design for manufacturability (DM guidelines, for futureintegrated circuit (IC) implementations.

There are several disadvantages to this approach. The most notoriousones are that DfM comes into play too late in the design stage, it ispassive as it is in the form of guidelines, and it may not be actual fornew very deep sub-micron technologies.

To overcome these limitations, the incorporation of design activitiesfor circuit performance and manufacturability (DfPM) prior to finishingof the IC is needed. Such activities aim at enabling circuit designtechnologies that are capable of attaining a required circuitmanufacturability and performance.

US 2002/0131314 describes a semiconductor device enjoying high stabilityand improved reliability by protecting the electrical characteristicsand the reliability against changes, notwithstanding a deviation orvariation in he condition of the fabrication process condition and theoperating condition. In order to obtain this, the operation voltageand/or operation current of circuits incorporated in the semiconductordevice are controlled in dependence on deviation or variation in thefabrication process condition and the operating condition. Thesemiconductor chip comprises a control circuit and an internal circuitinherent to a semiconductor device. The control circuit is provided forgenerating control signals or controlled internal voltages in accordancewith a deviation in the condition in the fabrication process as well asthe operating condition in which the semiconductor device is used. Thecharacteristics of the internal circuit can be maintained inpredetermined constant relationship in conformance with the fabricationprocess condition and the operating condition. The internal circuit maybe divided into several circuits each being provided with the respectivecontrol circuitry. In this case, the control can be achieved forrealizing the optimum operation characteristics for the individualfunctions of the divided circuitries.

It is an object of the present invention to provide an integratedcircuit with a global guaranteed level of performance, e.g. in terms ofboth speed and power, preferably independent of deviation or variationin the fabrication process condition and the operating condition.

The above objective is accomplished by a method and device according tothe present invention.

According to an aspect of the present invention, the adaptive behavioris carried out on a local basis. The system is partitioned intodifferent islands. Each can be contained in an isolated third well of atriple well CMOS technology. Triple well CMOS technology allows a wellof a first type, e.g. a P-well, to be placed inside a well of a secondtype, e.g. an N-well, resulting in three types of well structures:simple wells of the first type, simple wells of the second type, andwells of a third type, consisting of a wells of the first type inside adeep well of the second type. The third type of well is useful forisolating circuitry within it from other sections on the chip by areverse bias between the deep well of the second type and the substrate.Each well is controlled and its working conditions are modifieddepending on some parameters. The remainder of the chip is controlled aswell, depending on other parameters. This requires that each well has alocal controller communicating with a global controller. The maincontrol parameters may e.g. be supply voltage, threshold voltage andclock frequency.

The present invention provides an integrated circuit comprising aplurality of computation islands. Each computation island may compriseat least one processing core or module. Each computation island isoperating at one or more utility values, and at least one utility valueof a first computation island is different from a corresponding utilityvalue of a second computation island. The integrated circuit is providedwith monitoring means for monitoring at least one working parameterrelated to a working condition of the integrated circuit, and at leasttwo computation islands are provided with a local control device forindependently tuning at least one utility value for at least onecomputation island, based on the monitored at least one workingparameter. According to the present invention, the local control devicesare provided with communication means to communicate with a globalcontroller so as to obtain a pre-set level of performance of theintegrated circuit. It is an advantage of the present invention that theway of controlling described leads to an overall optimal performance ofthe IC, which is obtained by locally controlling a plurality of islands.So the overall performance of the IC is optimal, while the performanceof each of the islands is as optimal as possible, in view of the overallperformance.

The one or more utility values may comprise one or more of supply powerVdd, transistor threshold voltage Vt or clock frequency ck. Thetransistor threshold voltage Vt may be determined by a bulk voltage ofsome transistors in a computational island, e.g. the transistors of theprocessing core or module. The at least one working parameter related toa global working condition of the integrated circuit may comprise atleast one of circuit activity, circuit delay, power supply noise, logicnoise margin values, threshold voltage value or clock frequency value.The pre-set level of performance may relate to any or all of powerconsumption or speed of the integrated circuit.

Each computation island may be placed in an isolated third well of atriple-well CMOS technology.

An integrated circuit according to the present invention may furthermorecomprise at least one interface island for interfacing among computationislands, as the computation islands operate at different utility values,so direct interfacing between two computation islands might lead toproblems with regard to signal integrity. An interface island maycomprises at least a voltage level shifting device to translate voltagelevels from one computation island to another computation island. Aninterface island may furthermore comprise FIFOs for inter-islandcommunications.

At least two interface islands may be placed in a common third well, orsubstrate, of a triple-well CMOS technology. Preferably all interfaceislands are placed in one and the same common third well of atriple-well CMOS technology.

A computation island may furthermore comprise an actuator for tuning autility value in a monitored utility value-regulating closed-loopsystem. A computation island may furthermore comprise a local monitoringmeans for monitoring local working parameters of the computation island.

An integrated circuit according to the present invention may furthermorecomprise reference means for applying a power supply voltage referencevalue Vdd and/or a bulk voltage reference value V_(B) to the at leasttwo computation islands. The reference means may comprise a DC-DCconverter.

The present invention also provides a method for real-time tuning of atleast one utility value of an integrated circuit comprising a pluralityof computation islands. Each computation island may comprise at leastone processing core or module. Each computation island operates at oneor more utility values, at least one utility value of a firstcomputation island being different from a corresponding utility value ofa second computation island. At least two computation islands areprovided with a local control device for independently tuning at leastone utility value for at least one computation island. The methodcomprises monitoring of at least one working parameter related to aworking condition of the integrated circuit, based on the monitored atleast one working parameter, independently tuning at least one utilityvalue for at least one computation island by means of its localcontroller, and controlling the local controllers of the computationislands by means of a global controller so as to obtain a pre-set levelof performance of the integrated circuit.

The one or more utility values may comprise one or more of supply powerVdd, transistor threshold voltage Vt or clock frequency ck. The at leastone working parameter may comprise at least one of circuit activity,circuit delay, power supply noise, logic noise margin values, thresholdvoltage value, clock frequency value. The preset level of performancemay relate to any or all of power consumption or speed of the integratedcircuit.

The tuning of the utility value may be performed by changing the bulkvoltage V_(B) of some transistors in a computational island, e.g. in theprocessing core or module.

The integrated circuit may be designed based on utility values differentfrom their nominal values; what is also called a derated design.

These and other characteristics, features and advantages of the presentinvention will become apparent from the following detailed description,taken in conjunction with the accompanying drawings, which illustrate,by way of example, the principles of the invention. This description isgiven for the sake of example only, without limiting the scope of theinvention. The reference figures quoted below refer to the attacheddrawings.

FIG. 1 illustrates a span of design possibilities of a method accordingto an embodiment of the present invention.

FIG. 2 illustrates the concept of clustering of elements intocomputation islands and interface islands.

FIG. 3 is a block-schematic representation of an embodiment of acomputation island according to the present invention.

FIG. 4 illustrates an embodiment of a SoC implementing devices accordingto an embodiment of the present invention.

FIG. 5 illustrates power-delay iso-gradient contour plots over iso-powerdomains for a delay line circuit of eleven inverters in a 0.09 μm CMOStechnology.

FIG. 6 illustrates a state diagram of a local controller according to anembodiment of the present invention.

FIG. 7 illustrates a state diagram of delay check in a local controlleraccording to an embodiment of the present invention

FIG. 8 illustrates a state diagram of power check in a local controlleraccording to an embodiment of the present invention

FIG. 9 is a general circuit diagram for steepest descent

FIG. 10 illustrates transistor threshold voltage adaptation according toan embodiment of the present invention.

In the different figures, the same reference figures refer to the sameor analogous elements.

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes. Where the term “comprising” is used in thepresent description and claims, it does not exclude other elements orsteps. Where an indefinite or definite article is used when referring toa singular noun e.g. #“a” or “an”, “the”, this includes a plural of thatnoun unless something else is specifically stated.

The terms first, second, third and the like in the description and inthe claims, are used for distinguishing between similar elements and notnecessarily for describing a sequential or chronological order. It is tobe understood that the terms so used are interchangeable underappropriate circumstances and that the embodiments of the inventiondescribed herein are capable of operation in other sequences thandescribed or illustrated herein.

According to the present invention, an integrated circuit (IC), e.g. acore (or Intellectual Property (IP) module) or a system-on-chip (SoC) isadapted so that a certain level of performance is guaranteed. In thefollowing the word “chip” will be used to describe any of: IP module,system-on-chip, integrated circuit . . . . “A certain level ofperformance” means operating to with a certain operational constraint orto achieve a certain performance, e.g. in terms of any or both of speedand power consumption. This may be done by modifying the chip's workingconditions by varying any of its utility values, such as e.g. supplyvoltage or current, transistor threshold voltage, or frequency.According to the present invention, such adaptive behavior is not on aglobal basis, but it is achieved with locality. Preferably, the chip ispartitioned into different islands, e.g. logic in an IP, and IPs in anSoC. Preferably, each island is contained in an isolated third (e.g.deep-N) well of a triple-well CMOS technology. All the logic requiredfor the chip timing closure, such as e.g. registers for an IP orcommunication infrstructure for an SoC, goes outside these wells.

Each well is controlled by a local controller, and its workingconditions are modifiable depending upon the activity of the logic inthe well itself, for example, according to the noise margin related tothe signals traveling in the well. The modification is carried out withrespect to the global level of performance, e.g. with regard to powerconsumption and/or speed of the chip, in mind.

Preferably, everything outside the well is controlled depending upon anexternal reference giving an index for global chip activity and processcorner and working conditions.

Therefore, according to an aspect of the present invention, each wellhas a local controller communicating with a further controller such asglobal controller. The further controller also features distributedmonitoring for the logic outside the well so as to consider the averagelevel of performance values instead of local instantaneous values. Threemain control parameters can be identified: supply voltage, transistorthreshold voltage and clock frequency.

A method according to the present invention is a tuning scheme aimed atoptimizing the performance of a chip, e.g. of at least one IP, onlineand in real-time. When applied, it finds the chip's, e.g. the IC's orIP's, optimum power supply (Vdd), transistor threshold voltage (Vt) andclock frequency (ck), henceforth called utility values or optimizationvariables, for a given desired performance in terms of speed and/orpower consumption. The method according to the present invention sensesthe chip's, e.g. IP's or IC's, working parameters such as processspread, the electrical activity, a delay of a circuit and/or a powersupply noise of a circuit, and adjusts accordingly the optimizationvariables provided that the IC's or IP's signal integrity is notcompromised. The latter may be checked through a noise-margin monitor.The method searches an optimum power-delay product given the constraintsimposed by the process spread. By tuning the power supply Vdd and thetransistor threshold voltage Vt, there is also the possibility ofminimizing the IC's or IP's leakage current in a standby mode. Theutility values can be changed over a continuous range of values betweena minimum value and a maximum value for each utility value.

In FIG. 1 the power-delay curve 2 of an IC or IP is depicted when alltransistors have a nominal transistor threshold voltage Vt. FIG. 1 alsodisplays the opportunities for design under the method of the presentinvention, namely power, process, speed and leakage tuning. The uppercurve 4 in FIG. 1 corresponds to a power-delay curve when alltransistors have the highest possible Vt The lower curve 6 is apower-delay curve for a condition corresponding to the lowest allowableVt for all transistors.

The method of the present invention can also be used for derateddesigns. Because of variability of a fabrication process, every chip ina wafer is different from the others. Typically, a wafer is divided invarious regions yielding “slow”, “nominal”, and “fast” transistors.Conventional design methodologies make use of “nominal” conditions tocarry out the design. However, because under the present invention it ispossible to control the chip's utility values, it is thus possible todesign the chip, under, say, the “slow” condition using power supplyvalues Vdd and transistor threshold values Vt other than the nominalones and still meet the required performance. This is referred to as“derated designs”. The advantage of designing under the slow conditionis that the leakage current is much less because the transistorthreshold voltage is typically high. Under this concept it is possibleto synthesize an IC or an IP using a Vdd-Vt-clock frequency tripletother than the nominal points bringing new opportunities forpower-delay-area trade-offs.

From a system standpoint, the present invention provides an SoC (SystemOn Chip) composed of a plurality of islands. An island is composed ofone or more IPs or modules that have common electrical and activitycharacteristics. This partitioning into islands can be obtained at thehardware/software co-design partitioning stage. A distinction betweendifferent types of islands is made: there are interface islands andcomputation islands. Computation islands are electrically independent,e.g. each island has a distinct power supply value Vdd, transistorthreshold voltage Vt, and/or clock frequency ck. Two IP's belonging tothe same island have the same Vdd-Vt-ck triplet Interface islands areaware of the distinct electrical characteristics of the variouscomputation islands.

FIG. 2 shows an example of the island concept in which five IPs, IP1,IP2, IP3, IP4 and IP5, are clustered together into three distinctcomputation islands illustrated by different ways of hatching. IP1 andIP3 belong to a first computation island, IP2 and IP5 belong to a secondcomputation island, and IP4 belongs to a third computation island.Vertically hatched blocks are used to represent the interface islands.Since each computation island can have unique electricalcharacteristics, they communicate to each other through the interfaceislands (hatched vertically). These interface islands take care ofinterfacing the distinctive electrical characteristics of thecomputation islands as to avoid data synchronization errors and signalintegrity violations.

In a device according to the present invention, an integrated circuitcomprises a plurality of computation islands. Each computation islandcomprises, next to one or more IPs, means for monitoring at least oneworking parameter related to a working condition of the integratedcircuit These means for monitoring at least one working parameterrelated to a working condition of the integrated circuit may includeprocess, activity, and/or noise monitors. Each computation island alsocomprises actuators to adapt the utility values or optimizationvariables. Each computation island furthermore comprises a localcontroller. It is to be noted that the present invention is not intendedfor power management. Instead, it only adapts an IP to a desiredperformance decided upon by some other unit like a power managementunit.

FIG. 3 illustrates a computation island 30 comprising a single IP 32.Local actuators 34 adjust power supply voltage Vdd, transistor thresholdvoltage Vt and the clock frequency ck for this island 30 followingorders from a (local) island controller 36. In turn, the islandcontroller 36 decides upon the output of local monitors 38 the range towhich the local actuators 34 can be controlled. The interface islands 39remember the electrical characteristics of the IP 32 in this computationisland 30.

FIG. 4 shows an embodiment of an SoC 40 with a plurality of computationislands 30 and interface islands 39 according to an embodiment of thepresent invention. Each computation island 30 comprises at least one IP32. Each of the computation islands 30 is as explained with respect toFIG. 3. A root controller or global controller 42 is interfaced to eachof the local island controllers 36 by interfacing means such as a bus 44for example. For simplicity, each island 30 comprises only one IP 32 inFIG. 4, but this example is not intended to limit the invention thereto.The root controller 42 regulates the performance of the entire SoC 40and as such of each individual island 30. The root controller 42 decidesupon the output of global monitors 43 the range to which the islandcontrollers 36 can set the local actuators 34. The interface islands 39between islands 30 may be implemented in any suitable manner, forexample through FIFOS and using a technique called GALS (Globallyasynchronous, locally synchronous). In this way, every island 30 is keptcompletely autonomous from the others. A DC/DC converter 48, althoughnot necessary, may be provided for broadcasting a general power supplyvalue Vdd and bulk voltage Vb reference. The threshold voltage Vt of thetransistors is changed by properly biasing their bulk terminal. Thistechnique is commonly referred to as “back-gate biasing”. A transistor'sbulk terminal is connected to the well where the transistor resides. Forinstance PMOS transistors reside in an N-Well (assuming again atriple-well CMOS technology). By biasing the well, e.g. the bulkterminal, the threshold voltage characteristics of all transistors inthat well are automatically changed. A reference performance is appliedto the root controller so that it can optimize the overall ICperformance. The root controller keeps track of the performance of eachisland and functions according to a prescribed power managementalgorithm.

An example of applying a method according to principles of the presentinvention is illustrated in FIG. 5. It shows iso-gradient contour curvesof delay (dotted lines) over iso-power domains for a delay line circuitcomprising eleven inverters in a 0.09 μm CMOS technology. NMOS and PMOSthreshold voltages for a typical and a slow process corner are alsoshown. This example demonstrates that with a method according to thepresent invention it is possible to tune a circuit such that, despitethe fact that it was processed in a slow corner, its performance iscomparable to one processed in a typical corner. Typically, 0 V would beapplied to the P-well and 1 V would be applied to the N-well. When thisis done, however, as shown in point 50 on FIG. 5, the system has a delaybetween 550 ps and 600 ps, which is slow. In order to obtain performancein the typical corner, the wells of the circuit are adapted tocompensate for the process spread. This is achieved by applying 635 mVinstead of 1 V to the N-well to lower the transistor threshold Vtp ofPMOS transistors from 311 mV to 270 mV, and by applying 75 mV instead of0 V to the P-well to lower the transistor threshold Vtn of NMOStransistors from 250 mV to 240 mV, as shown in point 52 on FIG. 5.

An example of a local island controller implementation is givenhereinafter. This is one example only, and it is not intended to limitthe invention to this implementation. In the forthcoming illustrations,all reference values are assumed to have been broadcasted by the rootcontroller.

FIG. 6 depicts a state diagram of a local island controller. The actualimplementation can be done using any synthesis method. The logic behindthe diagram given is as follows. Before adapting any of the utilityvalues, a check 60 against the current noise margin is done to safeguardsignal integrity. If the result 61 is that the current noise margin islarger than an upper noise limit NU, there is a potential risk, and thesystem locks in an “alert” state 62. If not, the result 63 of the check60 is that the current noise margin is smaller than an upper noise limitNU, and the system comes in a “noise checked state” 64.

A delay check 65, a power check 66 and an activity check 67 areperformed. If the delay is larger than the maximum delay Dmax, thesystem has to be speed up, an in the delay is smaller than the minimumdelay, the system has to be slowed down. This is explained in moredetail hereinafter with respect to a finite state machine illustrated inFIG. 7. On the other hand, if the power consumption is larger than themaximum power Pmax, the power consumption has to be brought down. Thisis illustrated in FIG. 8.

The delay finite state machine shown in FIG. 7 has a bifurcation betweenspeeding up or slowing down the system. The local island controllerexpects from the root controller the maximum delay (Dmax) and minimumdelay (Dmin) specs, as well as the maximum power (Pmax) and minimumpower (Pmin) specs.

If the IP of the island does not meet the delay specs because the delayof the IP or plurality of IPs of the island considered is larger thanthe maximum delay Dmax of the system, a state indicated with 70 in FIG.7 is reached. The local island controller proceeds to adjust the IP'sdelay provided that the power budget is not exceeded. Therefore, theIP's power budget is compared with the maximum power Pmax and with theminimum power Pmin. If the IP's power exceeds the maximum power Pmax,the system locks in an alert state 71 because the system exceeds theupper power budget. If not, i.e. the IP's power budget is smaller thanthe minimum power Pmin, then the finite state machine reaches state 72.

The local island controller adjusts first the threshold voltage Vt andsubsequently the power supply. As long as Vt is larger than the lowerlimit of the threshold voltage, Vt can be adjusted and brought down.When Vt becomes equal to the lower limit VtL, then as long as the powersupply value Vdd is lower than the upper limit VddU of the power supplyvalue, Vdd can be raised. When Vdd becomes equal to VddU, the upperpower supply limit VddU is exceeded, and the system locks in an alertstate 73. VtU, VtL, VddU and VddL are the upper and lower limits of thethreshold voltage and of the power supply.

On the other hand, if the IP of the island does not meet the delay specsbecause the delay of the IP or plurality of IPs of the island consideredis smaller than the minimum delay Dmin of the system, a state indicatedwith 74 in FIG. 7 is reached.

The local island controller adjusts first the transistor thresholdvoltage Vt and subsequently the power supply. As long as Vt is smallerthan the upper limit VtU of the threshold voltage, Vt can be adjusted byraising it (state 75). When Vt becomes equal to the upper limit VtU,then as long as the power supply value Vdd is higher than the lowerlimit VddL of the power supply value, Vdd can be decreased, as indicatedwith the state indicated with 76 in FIG. 7. When Vdd becomes equal tothe lower power supply limit VddL, this lower power supply limit VddL isexceeded, and the system locks in an alert state 77.

The power check 66 shown in FIG. 8 is done only in cases when the powerconsumption exceeds its upper limit Pmax. Power adjustments are doneprovided that the circuit's delay is not compromised. The adaptationstrategy is similar to the delay check as explained with regard to FIG.7. Here again the transistor threshold voltage Vt is adapted first andthen the power supply value Vdd.

If the power consumption exceeds the maximum limit of the powerconsumption Pmax, state 80 is reached. If the delay is smaller than theminimum delay Dmin the system exceeds the speed lower limit and locks instate 81. If not, i.e. if the delay of the system is larger than theminimum delay Dmin, then state 82 is reached. In first instance, as longas the transistor threshold voltage Vt is smaller than the upper limitVtU of the threshold voltage, Vt is adjusting by increasing it (state83). As soon as Vt becomes equal to the upper limit VtU, then as long asthe power supply value Vdd is higher than the lower limit VddL of thepower supply value, Vdd can be decreased, as indicated with the stateindicated with 84 in FIG. 8. When Vdd becomes equal to the lower powersupply limit VddL, this lower power supply limit VddL is exceeded, andthe system locks in an alert state 85.

The optimization variables or utility supply variables, i.e. Vdd, Vt andthe clock frequency ck, can be optimized using general schemes like anygradient method such as, but not limited to, the steepest descent forexample. This can formulated as$\frac{\mathbb{d}x_{i}}{\mathbb{d}t} = {{- \mu}\quad(t)\frac{\partial{E(x)}}{\partial x_{i}}}$where the cost function E(x) is optimized subject to x_(i). FIG. 9 showsa general example of optimization using the steepest descent. Steepestdescent is a mathematical method for unconstrained optimization. Thismethod transforms the minimization problem to be solved into anassociated system of first order differential equations. The steepestdescent method finds an optimal x* that minimizes the function E(x). Theminima of the energy function is determined by following the solutioncurve (trajectory) of the gradient system withx*=lim _(t->∞) x(t)

FIG. 10 shows an example of threshold voltage adaptation using thesteepest descent method as in FIG. 9. Part of an island 30 is showncomprising an IP 32, a Vt monitor 100, a negative feedback integratorsystem 101, a switch 102 to start/stop the adaptation, a register 103and a D/A converter 104 and a controllable power supply 105 to adapt theIP's bulk to indirectly adjust the threshold voltage Vt. A referencetransistor threshold value VtR is one of the values broadcast by theroot controller. It is the value to which the transistor threshold valueof that particular island should be set. This value may be provided as adigital word and stored in the register 103. It may be converted to ananalog value via the D/A converter 104, compared in a comparator withthe actual value of the transistor threshold voltage, and the actualvalue of he transistor threshold voltage Vt may adjusted via thenegative feedback integrator system. In the above scheme it is expectedthat finite state machines shown in FIGS. 7-8 load the register 103 withthe reference voltage. For simplicity these finite state machines havebeen omitted in FIG. 10. It can be observed that the tuning itselfoccurs autonomously in an analog fashion. In this set-up it is assumedthat the threshold voltage Vt is adjusted through back biasingtechniques. V_(B) is a voltage controlled voltage source that is usedfor this purposes. Assuming that the IP has a threshold voltage Vt1distinct from the reference threshold voltage VtR. The actual thresholdvoltage of the IP is obtained through the Vt monitor as Vx. Thedifference of VtR and Vx is averaged through the integrator with a timeconstance μ so that an error signal ΔV is produced. If this signal iszero, V_(B) assumes its nominal value, meaning that V_(x) is identicalto VtR. If ΔV is different from zero, then V_(B) is adjusted accordinglyso that the Vt control system changes the IP's threshold voltage towardsthe reference value VtR.

It is to be understood that although preferred embodiments, specificconstructions and configurations have been discussed herein for methodsand devices according to the present invention, various changes ormodifications in form and detail may be made without departing from thescope and spirit of this invention.

1. An integrated circuit (40) comprising a plurality of computationislands (30), each computation island (30), each computation island (30)operating at one or more utility values, at least one utility value of afirst computation island being different from a corresponding utilityvalue of a second computation island, the integrated circuit (40) beingprovided with monitoring means (43) for monitoring at least one workingparameter related to a working condition of the integrated circuit (40),and at least two computation islands being provided with a local controldevice (36) for independently tuning at least one utility value for atleast one computation island, based on the monitored at least oneworking parameter, wherein the local control devices (36) are providedwith communication means to communicate with a global controller (42) soas to obtain a pre-set level of performance of the integrated circuit(40).
 2. An integrated circuit (40) according to claim 1, wherein theone or more utility values comprise one or more of supply power (Vdd),transistor threshold voltage (Vt) or clock frequency (ck).
 3. Anintegrated circuit (40) according to claim 2, wherein the transistorthreshold voltage is determined by a bulk voltage of some transistors ina computational island (30).
 4. An integrated circuit (40) according toclaim 1, wherein the at least one working parameter comprises at leastone of circuit activity, circuit delay, power supply noise, logic noisemargin values, threshold voltage value, clock frequency value.
 5. Anintegrated circuit (40) according to claim 1, wherein the pre-set levelof performance relates to any or all of power consumption or speed ofthe integrated circuit (40).
 6. An integrated circuit (40) according toclaim 1, wherein each computation island (30) is placed in an isolatedthird well of a triple-well CMOS technology.
 7. An integrated circuit(40) according to claim 1, furthermore comprising at least one interfaceisland (39) for interfacing among computation islands (30).
 8. Anintegrated circuit (40) according to claim 7, wherein at least twointerface islands (39) are placed in a common third well, or substrate,of a triple-well CMOS technology.
 9. An integrated circuit (40)according to claim 1, a computation island (30) furthermore comprisingan actuator (34) for tuning a utility value in a monitored utilityvalue-regulating closed-loop system.
 10. An integrated circuit (40)according to claim 1, a computation island (30) furthermore comprising alocal monitoring means (38) for monitoring local working parameters ofthe computation island (30).
 11. A method for real-time tuning of atleast one utility value of an integrated circuit (40) comprising aplurality of computation islands (30), each computation island (30)operating at one or more utility values, at least one utility value of afirst computation island being different from a corresponding utilityvalue of a second computation island, at least two computation islandsbeing provided with a local control device (36) for independently tuningat least one utility value for at least one computation island (30), themethod comprising monitoring of at least one working parameter relatedto a working condition of the integrated circuit (40), based on themonitored at least one working parameter, independently tuning at leastone utility value for at least one computation island (30) by means ofits local controller (36), and controlling the local controllers (36) ofthe computation islands (30) by means of a global controller (42) so asto obtain a pre-set level of performance of the integrated circuit (40).12. A method according to claim 11, wherein the one or more utilityvalues comprise one or more of supply power (Vdd), transistor thresholdvoltage (Vt) or clock frequency (ck).
 13. A method according to claim11, wherein the at least one working parameter comprises at least one ofcircuit activity, circuit delay, power supply noise, logic noise marginvalues, threshold voltage value, clock frequency value.
 14. A methodaccording to claim 11, wherein the pre-set level of performance relatesto any or all of power consumption or speed of the integrated circuit(40).
 15. A method according to claim 11, wherein the integrated circuit(40) is designed based on utility values different from their nominalvalues.